400 lines
13 KiB
Plaintext
400 lines
13 KiB
Plaintext
/* Copyright 2025 SGLang Team. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cuda.h>
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#include <cuda_fp8.h>
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#include <cuda_runtime.h>
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#include <cuda_runtime_api.h>
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#include <torch/all.h>
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#include "utils.h"
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// Get type2 from type or vice versa (applied to half and bfloat16)
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template <typename T>
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struct TypeConverter {
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using Type = half2;
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}; // keep for generality
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template <>
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struct TypeConverter<half2> {
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using Type = half;
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};
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template <>
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struct TypeConverter<half> {
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using Type = half2;
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};
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template <>
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struct TypeConverter<__nv_bfloat162> {
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using Type = __nv_bfloat16;
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};
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template <>
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struct TypeConverter<__nv_bfloat16> {
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using Type = __nv_bfloat162;
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};
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#define ELTS_PER_THREAD 8
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constexpr int CVT_FP4_ELTS_PER_THREAD = 8;
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constexpr int CVT_FP4_SF_VEC_SIZE = 16;
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// Convert 8 float32 values into 8 e2m1 values (represented as one uint32_t).
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inline __device__ uint32_t fp32_vec_to_e2m1(float (&array)[8]) {
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// PTX instructions used here requires sm100a.
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#if CUDA_VERSION >= 12080
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000) && __CUDA_ARCH_HAS_FEATURE__(SM100_ALL)
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uint32_t val;
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asm volatile(
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"{\n"
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".reg .b8 byte0;\n"
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".reg .b8 byte1;\n"
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".reg .b8 byte2;\n"
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".reg .b8 byte3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\n"
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"mov.b32 %0, {byte0, byte1, byte2, byte3};\n"
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"}"
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: "=r"(val)
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: "f"(array[0]),
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"f"(array[1]),
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"f"(array[2]),
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"f"(array[3]),
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"f"(array[4]),
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"f"(array[5]),
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"f"(array[6]),
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"f"(array[7]));
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return val;
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#else
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return 0;
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#endif
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#endif
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}
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// Convert 4 float2 values into 8 e2m1 values (represented as one uint32_t).
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inline __device__ uint32_t fp32_vec_to_e2m1(float2 (&array)[4]) {
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// PTX instructions used here requires sm100a.
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#if CUDA_VERSION >= 12080
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000) && __CUDA_ARCH_HAS_FEATURE__(SM100_ALL)
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uint32_t val;
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asm volatile(
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"{\n"
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".reg .b8 byte0;\n"
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".reg .b8 byte1;\n"
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".reg .b8 byte2;\n"
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".reg .b8 byte3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\n"
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"mov.b32 %0, {byte0, byte1, byte2, byte3};\n"
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"}"
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: "=r"(val)
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: "f"(array[0].x),
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"f"(array[0].y),
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"f"(array[1].x),
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"f"(array[1].y),
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"f"(array[2].x),
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"f"(array[2].y),
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"f"(array[3].x),
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"f"(array[3].y));
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return val;
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#else
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return 0;
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#endif
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#endif
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}
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// Fast reciprocal.
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inline __device__ float reciprocal_approximate_ftz(float a) {
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float b;
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asm volatile("rcp.approx.ftz.f32 %0, %1;\n" : "=f"(b) : "f"(a));
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return b;
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}
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template <class SFType, int CVT_FP4_NUM_THREADS_PER_SF>
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__device__ uint8_t* cvt_quant_to_fp4_get_sf_out_offset(int rowIdx, int colIdx, int numCols, SFType* SFout) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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static_assert(CVT_FP4_NUM_THREADS_PER_SF == 1 || CVT_FP4_NUM_THREADS_PER_SF == 2);
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// One pair of threads write one SF to global memory.
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// TODO: stage through smem for packed STG.32
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// is it better than STG.8 from 4 threads ?
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if (threadIdx.x % CVT_FP4_NUM_THREADS_PER_SF == 0) {
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// SF vector index (16 elements share one SF in the K dimension).
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int32_t kIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;
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int32_t mIdx = rowIdx;
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// SF layout [numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]
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// --> index [mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]
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int32_t mTileIdx = mIdx / (32 * 4);
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// SF vector size 16.
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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int32_t numKTiles = (numCols + factor - 1) / factor;
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int64_t mTileStride = numKTiles * 32 * 4 * 4;
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int32_t kTileIdx = (kIdx / 4);
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int64_t kTileStride = 32 * 4 * 4;
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// M tile layout [32, 4] is column-major.
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int32_t outerMIdx = (mIdx % 32);
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int64_t outerMStride = 4 * 4;
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int32_t innerMIdx = (mIdx % (32 * 4)) / 32;
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int64_t innerMStride = 4;
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int32_t innerKIdx = (kIdx % 4);
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int64_t innerKStride = 1;
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// Compute the global offset.
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int64_t SFOffset = mTileIdx * mTileStride + kTileIdx * kTileStride + outerMIdx * outerMStride +
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innerMIdx * innerMStride + innerKIdx * innerKStride;
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return reinterpret_cast<uint8_t*>(SFout) + SFOffset;
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}
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#endif
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return nullptr;
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}
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// Define a 16 bytes packed data type.
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template <class Type>
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struct PackedVec {
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typename TypeConverter<Type>::Type elts[4];
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};
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template <>
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struct PackedVec<__nv_fp8_e4m3> {
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__nv_fp8x2_e4m3 elts[8];
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};
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// Quantizes the provided PackedVec into the uint32_t output
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template <class Type, bool UE8M0_SF = false>
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__device__ uint32_t cvt_warp_fp16_to_fp4(PackedVec<Type>& vec, float SFScaleVal, uint8_t* SFout) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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// Get absolute maximum values among the local 8 values.
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auto localMax = __habs2(vec.elts[0]);
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// Local maximum value.
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#pragma unroll
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for (int i = 1; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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localMax = __hmax2(localMax, __habs2(vec.elts[i]));
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}
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// Get the absolute maximum among all 16 values (two threads).
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localMax = __hmax2(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);
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// Get the final absolute maximum values.
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float vecMax = float(__hmax(localMax.x, localMax.y));
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// Get the SF (max value of the vector / max value of e2m1).
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// maximum value of e2m1 = 6.0.
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// TODO: use half as compute data type.
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float SFValue = SFScaleVal * (vecMax * reciprocal_approximate_ftz(6.0f));
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// 8 bits representation of the SF.
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uint8_t fp8SFVal;
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// Write the SF to global memory (STG.8).
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if constexpr (UE8M0_SF) {
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__nv_fp8_e8m0 tmp;
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tmp.__x = __nv_cvt_float_to_e8m0(SFValue, __NV_SATFINITE, cudaRoundPosInf);
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SFValue = static_cast<float>(tmp);
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fp8SFVal = tmp.__x;
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} else {
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// Here SFValue is always positive, so E4M3 is the same as UE4M3.
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__nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);
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fp8SFVal = tmp.__x;
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SFValue = static_cast<float>(tmp);
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}
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// Get the output scale.
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// Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) *
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// reciprocal(SFScaleVal))
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float outputScale =
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SFValue != 0 ? reciprocal_approximate_ftz(SFValue * reciprocal_approximate_ftz(SFScaleVal)) : 0.0f;
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if (SFout) {
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// Write the SF to global memory (STG.8).
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*SFout = fp8SFVal;
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}
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// Convert the input to float.
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float2 fp2Vals[CVT_FP4_ELTS_PER_THREAD / 2];
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#pragma unroll
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for (int i = 0; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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if constexpr (std::is_same_v<Type, half>) {
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fp2Vals[i] = __half22float2(vec.elts[i]);
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} else {
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fp2Vals[i] = __bfloat1622float2(vec.elts[i]);
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}
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fp2Vals[i].x *= outputScale;
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fp2Vals[i].y *= outputScale;
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}
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// Convert to e2m1 values.
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uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);
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// Write the e2m1 values to global memory.
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return e2m1Vec;
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#else
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return 0;
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#endif
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}
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// Use UE4M3 by default.
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template <class Type, bool UE8M0_SF = false>
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__global__ void
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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__launch_bounds__(512, 4) cvt_fp16_to_fp4(
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#else
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cvt_fp16_to_fp4(
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#endif
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int32_t numRows, int32_t numCols, Type const* in, float const* SFScale, uint32_t* out, uint32_t* SFout) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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using PackedVec = PackedVec<Type>;
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static constexpr int CVT_FP4_NUM_THREADS_PER_SF = (CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD);
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static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD, "Vec size is not matched.");
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// Get the global scaling factor, which will be applied to the SF.
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// Note SFScale is the same as next GEMM's alpha, which is
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// (448.f / (Alpha_A / 6.f)).
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[0];
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// Input tensor row/col loops.
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for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {
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for (int colIdx = threadIdx.x; colIdx < numCols / CVT_FP4_ELTS_PER_THREAD; colIdx += blockDim.x) {
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int64_t inOffset = rowIdx * (numCols / CVT_FP4_ELTS_PER_THREAD) + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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// Get the output tensor offset.
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// Same as inOffset because 8 elements are packed into one uint32_t.
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int64_t outOffset = inOffset;
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auto& out_pos = out[outOffset];
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t, CVT_FP4_NUM_THREADS_PER_SF>(rowIdx, colIdx, numCols, SFout);
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out_pos = cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(in_vec, SFScaleVal, sf_out);
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}
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}
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#endif
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}
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template <typename T>
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void invokeFP4Quantization(
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int m,
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int n,
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T const* input,
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float const* SFScale,
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int64_t* output,
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int32_t* SFOuput,
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bool useUE8M0,
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int multiProcessorCount,
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cudaStream_t stream) {
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// Grid, Block size.
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// Each thread converts 8 values.
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dim3 block(std::min(int(n / ELTS_PER_THREAD), 512));
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// Get number of blocks per SM (assume we can fully utilize the SM).
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int const numBlocksPerSM = 2048 / block.x;
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dim3 grid(std::min(int(m), multiProcessorCount * numBlocksPerSM));
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// Launch the cvt kernel.
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if (useUE8M0) {
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cvt_fp16_to_fp4<T, true><<<grid, block, 0, stream>>>(
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m, n, input, SFScale, reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput));
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} else {
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cvt_fp16_to_fp4<T, false><<<grid, block, 0, stream>>>(
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m, n, input, SFScale, reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput));
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}
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}
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// Instantiate the function.
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template void invokeFP4Quantization(
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int m,
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int n,
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half const* input,
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float const* SFScale,
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int64_t* output,
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int32_t* SFOuput,
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bool useUE8M0,
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int multiProcessorCount,
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cudaStream_t stream);
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template void invokeFP4Quantization(
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int m,
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int n,
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__nv_bfloat16 const* input,
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float const* SFScale,
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int64_t* output,
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int32_t* SFOuput,
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bool useUE8M0,
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int multiProcessorCount,
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cudaStream_t stream);
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inline int getMultiProcessorCount() {
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static int multi_processor_count = []() {
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int device_id = 0;
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int count = 0;
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// Get the current CUDA device ID
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CHECK_CUDA_SUCCESS(cudaGetDevice(&device_id));
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// Get the number of multiprocessors for the current device
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CHECK_CUDA_SUCCESS(cudaDeviceGetAttribute(&count, cudaDevAttrMultiProcessorCount, device_id));
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return count; // Initialize the static variable
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}();
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return multi_processor_count; // Return the cached value on subsequent calls
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}
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void scaled_fp4_quant_sm100a(
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torch::Tensor& output, torch::Tensor const& input, torch::Tensor& output_sf, torch::Tensor const& input_sf) {
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int32_t m = input.size(0);
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int32_t n = input.size(1);
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TORCH_CHECK(n % 16 == 0, "The N dimension must be multiple of 16.");
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int multiProcessorCount = getMultiProcessorCount();
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auto input_sf_ptr = static_cast<float const*>(input_sf.data_ptr());
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auto sf_out = static_cast<int32_t*>(output_sf.data_ptr());
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auto output_ptr = static_cast<int64_t*>(output.data_ptr());
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at::cuda::CUDAGuard device_guard{(char)input.get_device()};
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream(input.get_device());
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// We don't support e8m0 scales at this moment.
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bool useUE8M0 = false;
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switch (input.scalar_type()) {
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case torch::kHalf: {
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auto input_ptr = reinterpret_cast<half const*>(input.data_ptr());
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invokeFP4Quantization(m, n, input_ptr, input_sf_ptr, output_ptr, sf_out, useUE8M0, multiProcessorCount, stream);
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break;
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}
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case torch::kBFloat16: {
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auto input_ptr = reinterpret_cast<__nv_bfloat16 const*>(input.data_ptr());
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invokeFP4Quantization(m, n, input_ptr, input_sf_ptr, output_ptr, sf_out, useUE8M0, multiProcessorCount, stream);
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break;
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}
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default: {
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std::cerr << "Observing: " << input.scalar_type() << " for the input datatype which is invalid";
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throw std::runtime_error("Unsupported input data type for quantize_to_fp4.");
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}
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}
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}
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