198 lines
8.9 KiB
Plaintext
198 lines
8.9 KiB
Plaintext
/*
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* Copyright (c) 2023 by FlashInfer team.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <flashinfer/attention/scheduler.cuh>
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#include <flashinfer/pos_enc.cuh>
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#include <flashinfer/utils.cuh>
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#include <optional>
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#include "batch_decode_config.inc"
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#include "pytorch_conversion_utils.h"
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#include "pytorch_extension_utils.h"
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namespace flashinfer {
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template <uint32_t HEAD_DIM, PosEncodingMode POS_ENCODING_MODE, typename AttentionVariant,
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typename Params>
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cudaError_t BatchDecodeWithPagedKVCacheDispatched(Params params, typename Params::DTypeO* tmp_v,
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float* tmp_s, bool enable_pdl,
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cudaStream_t stream);
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} // namespace flashinfer
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using namespace flashinfer;
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at::Tensor BatchDecodeWithPagedKVCachePlan(
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at::Tensor float_workspace_buffer, at::Tensor int_workspace_buffer,
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at::Tensor page_locked_int_workspace_buffer, at::Tensor indptr, int64_t batch_size,
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int64_t num_qo_heads, int64_t num_kv_heads, int64_t page_size, bool enable_cuda_graph,
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int64_t window_left, double logits_soft_cap, int64_t head_dim_qk, int64_t head_dim_vo,
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at::Tensor empty_q_data, at::Tensor empty_kv_data) {
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size_t float_workspace_size_in_bytes =
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float_workspace_buffer.size(0) * float_workspace_buffer.element_size();
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size_t int_workspace_size_in_bytes =
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int_workspace_buffer.size(0) * int_workspace_buffer.element_size();
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DecodePlanInfo plan_info;
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auto q_scalar_type = empty_q_data.scalar_type();
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auto kv_scalar_type = empty_kv_data.scalar_type();
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TORCH_CHECK(head_dim_qk == head_dim_vo,
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"CUDA cores template only supports equal head dim for QK and VO, please use tensor "
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"cores template for different head dim");
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const c10::cuda::OptionalCUDAGuard device_guard(float_workspace_buffer.device());
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const cudaStream_t stream = c10::cuda::getCurrentCUDAStream();
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DISPATCH_context(
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DTypeQ, DTypeKV, DTypeO, IdType, HEAD_DIM_QK, HEAD_DIM_VO, POS_ENCODING_MODE,
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USE_SLIDING_WINDOW, USE_LOGITS_SOFT_CAP, AttentionVariant, Params, [&] {
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DISPATCH_GQA_GROUP_SIZE(num_qo_heads / num_kv_heads, GROUP_SIZE, {
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auto work_estimation_func = BatchDecodeWithPagedKVCacheWorkEstimationDispatched<
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GROUP_SIZE, HEAD_DIM_QK, POS_ENCODING_MODE, AttentionVariant, Params>;
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cudaError_t status = DecodePlan<HEAD_DIM_QK, POS_ENCODING_MODE, AttentionVariant, Params>(
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static_cast<void*>(float_workspace_buffer.data_ptr()), float_workspace_size_in_bytes,
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static_cast<void*>(int_workspace_buffer.data_ptr()),
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static_cast<void*>(page_locked_int_workspace_buffer.data_ptr()),
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int_workspace_size_in_bytes, plan_info, static_cast<IdType*>(indptr.data_ptr()),
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batch_size, num_qo_heads, page_size, enable_cuda_graph,
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/*stream=*/stream, work_estimation_func);
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TORCH_CHECK(status == cudaSuccess, "BatchDecodeWithPagedKVCache failed with error ",
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cudaGetErrorString(status));
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return true;
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});
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});
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return vec_to_tensor(plan_info.ToVector());
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}
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void BatchDecodeWithPagedKVCacheRun(at::Tensor float_workspace_buffer,
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at::Tensor int_workspace_buffer, at::Tensor plan_info_vec,
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at::Tensor q, at::Tensor paged_k_cache,
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at::Tensor paged_v_cache, at::Tensor paged_kv_indptr,
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at::Tensor paged_kv_indices, at::Tensor paged_kv_last_page_len,
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at::Tensor o, std::optional<at::Tensor> maybe_lse,
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int64_t kv_layout_code, int64_t window_left,
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bool enable_pdl ADDITIONAL_FUNC_PARAMS) {
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DecodePlanInfo plan_info;
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plan_info.FromVector(tensor_to_vec(plan_info_vec));
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QKVLayout kv_layout = static_cast<QKVLayout>(kv_layout_code);
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auto device = q.device();
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int64_t batch_size = q.size(0);
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int64_t num_qo_heads = q.size(1);
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int64_t num_kv_heads, page_size;
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if (kv_layout == QKVLayout::kHND) {
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num_kv_heads = paged_k_cache.size(1);
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page_size = paged_k_cache.size(2);
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} else {
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page_size = paged_k_cache.size(1);
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num_kv_heads = paged_k_cache.size(2);
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}
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uint32_t head_dim_qk = q.size(2);
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uint32_t head_dim_vo = paged_v_cache.size(3);
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TORCH_CHECK(head_dim_qk == head_dim_vo,
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"CUDA cores template only supports equal head dim for QK and VO, please use tensor "
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"cores template for different head dim");
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if (maybe_lse) {
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const auto& lse = *maybe_lse;
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TORCH_CHECK(lse.size(0) == batch_size, lse.size(0), q.size(0));
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TORCH_CHECK(lse.size(1) == num_qo_heads, lse.size(1), q.size(1));
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}
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void* float_buffer = static_cast<void*>(float_workspace_buffer.data_ptr());
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void* int_buffer = static_cast<void*>(int_workspace_buffer.data_ptr());
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// get q_scalar_type and kv_scalar_type
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auto q_scalar_type = q.scalar_type();
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auto kv_scalar_type = paged_k_cache.scalar_type();
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// get q_stride_n and q_stride_h
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const auto q_stride_n = q.stride(0);
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const auto q_stride_h = q.stride(1);
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// get kv_cache_strides
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const int64_t* kv_cache_strides = nullptr;
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auto k_strides = paged_k_cache.strides();
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auto v_strides = paged_v_cache.strides();
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TORCH_CHECK(k_strides == v_strides, "k/v strides must be identical");
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kv_cache_strides = k_strides.data();
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const c10::cuda::OptionalCUDAGuard device_guard(device);
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const cudaStream_t stream = c10::cuda::getCurrentCUDAStream();
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DISPATCH_context(
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DTypeQ, DTypeKV, DTypeO, IdType, HEAD_DIM_QK, HEAD_DIM_VO, POS_ENCODING_MODE,
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USE_SLIDING_WINDOW, USE_LOGITS_SOFT_CAP, AttentionVariant, Params, [&] {
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paged_kv_t<DTypeKV, IdType> paged_kv(
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num_kv_heads, page_size, HEAD_DIM_QK, batch_size, kv_layout,
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static_cast<DTypeKV*>(paged_k_cache.data_ptr()),
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static_cast<DTypeKV*>(paged_v_cache.data_ptr()), kv_cache_strides,
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static_cast<IdType*>(paged_kv_indices.data_ptr()),
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static_cast<IdType*>(paged_kv_indptr.data_ptr()),
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static_cast<IdType*>(paged_kv_last_page_len.data_ptr()));
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Params params;
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params.q = static_cast<DTypeQ*>(q.data_ptr());
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params.paged_kv = paged_kv;
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params.o = static_cast<DTypeO*>(o.data_ptr());
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params.lse = maybe_lse ? static_cast<float*>(maybe_lse->data_ptr()) : nullptr;
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params.padded_batch_size = 0;
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params.num_qo_heads = num_qo_heads;
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params.q_stride_n = q_stride_n;
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params.q_stride_h = q_stride_h;
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params.window_left = window_left;
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params.request_indices = nullptr;
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params.kv_tile_indices = nullptr;
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params.o_indptr = nullptr;
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params.kv_chunk_size_ptr = nullptr;
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params.block_valid_mask = nullptr;
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params.partition_kv = false;
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ADDITIONAL_PARAMS_SETTER
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DTypeO* tmp_v = nullptr;
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float* tmp_s = nullptr;
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params.request_indices =
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GetPtrFromBaseOffset<IdType>(int_buffer, plan_info.request_indices_offset);
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params.kv_tile_indices =
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GetPtrFromBaseOffset<IdType>(int_buffer, plan_info.kv_tile_indices_offset);
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params.o_indptr = GetPtrFromBaseOffset<IdType>(int_buffer, plan_info.o_indptr_offset);
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params.kv_chunk_size_ptr =
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GetPtrFromBaseOffset<IdType>(int_buffer, plan_info.kv_chunk_size_ptr_offset);
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if (plan_info.split_kv) {
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tmp_v = GetPtrFromBaseOffset<DTypeO>(float_buffer, plan_info.v_offset);
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tmp_s = GetPtrFromBaseOffset<float>(float_buffer, plan_info.s_offset);
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if (plan_info.enable_cuda_graph) {
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params.block_valid_mask =
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GetPtrFromBaseOffset<bool>(int_buffer, plan_info.block_valid_mask_offset);
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}
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}
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params.padded_batch_size = plan_info.padded_batch_size;
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cudaError_t status =
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flashinfer::BatchDecodeWithPagedKVCacheDispatched<HEAD_DIM_QK, POS_ENCODING_MODE,
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AttentionVariant>(params, tmp_v,
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tmp_s, enable_pdl,
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/*stream=*/stream);
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TORCH_CHECK(status == cudaSuccess, "BatchDecodeWithPagedKVCache failed with error ",
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cudaGetErrorString(status));
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return true;
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});
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}
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